Answer by Im Groot for How do I call a module repeatedly in Verilog, in sync...
First, apart from your basic question about calling a module repeatedly in Verilog, there are alot of mistakes in your code:address is not being driven by any logic.value1 is not declared anywhere in...
View ArticleHow do I call a module repeatedly in Verilog, in sync with a clock?
What I intend to do is basically cycle through a LUT created in a second module, by instantiating it in the first. Additionally, I need to call the instantiation in sync with the clock.The basic idea...
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